Violin Memory V-6264-НА 64

U-Boot 2009.11 supervisor A5.0.4 #1-prealpha ppc acm chann@eng-bui (Aug 01 2011 - 10:55:59)

CPU0:  P2020E, Version: 2.1, (0x80ea0021)
Core:  E500, Version: 5.1, (0x80211051)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz,
       CCB:400  MHz,
       DDR:200  MHz (400 MT/s data rate) (Synchronous), LBC:25   MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: Violin P2020 ACM-B Rev -
FPGA:  Kazoo Rev12a
FPGA:  Bagpipe Version-L V01.87 Build: Jun 11 2012 11:55:41

I2C:   ready
DRAM:  Configuring DDR for 400 MT/s data rate
DDR:  2 GB
Reserving 918k for U-Boot at: 7ff10000
FLASH: 16 MB
L2:    512 KB enabled
MMC:  FSL_ESDHC: 0
    eTSEC2 is in sgmii mode.
    eTSEC3 is in sgmii mode.

    PCIE1 used as Root Complex (base addr ffe0a000)
               Scanning PCI bus 01
        01  00  10b5  8696  0604  00
    PCIE1 on bus 00 - 02

    PCIE2: disabled

In:    serial
Out:   serial
Err:   serial
Configuring GIGE Switch Port 0......Configured
Configuring GIGE Switch Port 1......Configured
Configuring GIGE Switch Port 2......Configured
Configuring GIGE Switch Port 3......Configured
Configuring GIGE Switch Port 4......Configured
Configuring GIGE Switch Port 5......Configured
Configuring GIGE Switch Port 6......Configured
Configuring GIGE Switch Port 7......Configured
Net:   eTSEC2: No support for PHY id ffffffff; assuming generic
eTSEC1, eTSEC2, eTSEC3
Reset RTC...
Date: 2025-06-25 (Wednesday)    Time:  4:11:47
Reading image settings
Reading image settings 'a'
Card did not respond to voltage select!
MMC init failed
Reading image settings 'b'
Card did not respond to voltage select!
MMC init failed
Error parsing image settings.
Error reading boot menu settings.