Флаги в ssp_config

pxa_gpio_mode(GPIO_ROVERS5_TSC2101_SS | GPIO_OUT | GPIO_DFLT_HIGH);
gpio_set_value(GPIO_ROVERS5_TSC2101_PWR, 0);
gpio_set_value(GPIO_ROVERS5_TSC2101_PWR, 1); 	gpio_set_value(GPIO_ROVERS5_TSC2101_RESET, 0);	
gpio_set_value(GPIO_ROVERS5_TSC2101_RESET, 1);	
...
ssp_disable(&rovers5_ssp_dev3);
ssp_config(&rovers5_ssp_dev3, (SSCR0_Motorola | SSCR0_DataSize(0x0f)), SSCR1_SPH, 0, SSCR0_SerClkDiv(6));
ssp_enable(&rovers5_ssp_dev3);

gpio_set_value(GPIO_ROVERS5_TSC2101_SS, 0);	
ssp_write_word(&rovers5_ssp_dev3, command | read);
ssp_read_word(&rovers5_ssp_dev3, &ret);
for (i=0; i < numval; i++) {
	if (read) {
		ssp_write_word(&rovers5_ssp_dev3, 0);
		ssp_read_word(&rovers5_ssp_dev3, &values[i]);
	} else {
		ssp_write_word(&rovers5_ssp_dev3, values[i]);
		ssp_read_word(&rovers5_ssp_dev3, &ret);
	}
}
gpio_set_value(GPIO_ROVERS5_TSC2101_SS, 1);

RESET
    The device requires reset after power up. This requires a low-to-high transition on the RESET pin after power
    up for correct operation. Reset initializes all the internal registers, counters and logic.
Hardware Power-Down
    Hardware power-down powers down all the internal circuitry to save power. All the register contents are
    maintained. Putting the TSC2101 into hardware power-down circuit also disables the pen-touch detect circuit.
General Purpose I/O
    The TSC2101 has two general purpose I/O (GPIO1 and GPIO2), which can be programmed either as inputs
    or outputs. As outputs they can be programmed to control external logic through the TSC2101 registers or send
    interrupts to the host processor on events like button detect, headset insertion, headset removal,
    Auxiliary/temperature outside threshold range etc. As inputs they can be used by the host-processor to monitor
    logic states of signals on the system through the TSC2101 registers.
SPI Digital Interface
     All TSC2101 control registers are programmed through a standard SPI bus. The SPI allows full-duplex,
     synchronous, serial communication between a host processor (the master) and peripheral devices (slaves).
     The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on 
     a master to start and synchronize transmissions.
     A transmission begins when initiated by a master SPI. The byte from the master SPI begins shifting in on the 
     slave MOSI pin under the control of the master serial clock. As the byte shifts in on the MOSI pin, a byte 
     shifts out on the MISO pin to the master shift register.
     The idle state of the serial clock for the TSC2101 is low, which corresponds to a clock polarity setting of 0 
     (typical microprocessor SPI control bit CPOL = 0). The TSC2101 interface is designed so that with a clock 
     phase bit setting of 1 (typical microprocessor SPI control bit CPHA = 1), the master begins driving its MOSI 
     pin and the slave begins driving its MISO pin on the first serial clock edge. The SS pin can remain low 
     between transmissions; however, the TSC2101 only interprets command words which are transmitted after the 
     falling edge of SS.
Register Programming
     The TSC2101 is entirely controlled by registers. Reading and writing these registers is controlled by an SPI 
     master and accomplished by the use of a 16-bit command, which is sent prior to the data for that register.
     The command word begins with an R/W bit, which specifies the direction of data flow on the SPI serial bus. 
     The following 4 bits specify the page of memory this command is directed to, as shown in Table 5. The next 
     six bits specify the register address on that page of memory to which the data is directed. The last five 
     bits are reserved for future use and should be written only with zeros.