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https://www.ti.com/lit/an/spracv1/spracv1.pdf

LMBench benchmark lat_mem_rd is used to measure observed memory access latency for external memory(DDR4/LPDDR4 on AM64x) and cache hits. The two arguments are size of of the transaction (64 in thescreenshot below) and the stride of the read (512). These two values are selected to measure the latency tocaches and external memory not the processor data prefetchers or other speculative execution. For someaccess patterns the prefetcing will work, but this benchmark is most useful to measure the case when it doesnot. The left column is the size of the data access pattern in megabytes, right column is the round trip readlatency in nanoseconds. As a summary for Arm Cortex-A53 latency to L1D is 3 ns, L2 latency is 14 ns, andaccess to DDR4 is 196 ns.
root@am6x-evm:~# lat_mem_rd 64 512
"stride=512
0.00049 3.006
0.00098 3.006
0.00195 3.006
0.00293 3.006
0.00391 3.006
0.00586 3.006
0.00781 3.006
0.01172 3.006
0.01562 3.006
0.02344 3.009
0.03125 3.120
0.04688 9.212
0.06250 10.677
0.09375 12.269
0.12500 12.984
0.18750 13.651
0.25000 14.066
0.37500 115.226
0.50000 168.747
0.75000 189.919
1.00000 192.138
1.50000 193.431
2.00000 194.175
3.00000 194.870
4.00000 195.202
6.00000 195.463
8.00000 195.622
12.00000 195.700
16.00000 195.761
24.00000 195.876
32.00000 195.938
48.00000 196.001
64.00000 196.006
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