Два сегмента по одному адресу

MEMORY
{
	RAM (rwx)	: ORIGIN = 0x20000000, LENGTH = 6K
	FLASH (rx)	: ORIGIN = 0x08000000, LENGTH = 16K
}

SECTIONS
{
	.isr : ALIGN(4)
	{
		ld_sisr = . ;

		KEEP(*(.isr))

	} > RAM

	.text : ALIGN(4)
	{
		*(.text)
		*(.text.*)
		*(.rodata)
		*(.rodata.*)
 
		. = ALIGN(4);
		ld_etext = . ;

	} > RAM

	...

.syntax unified
.cpu cortex-m3
.thumb

.section .isr

	.word 0
	.word isr_reset
	.word 0
	.word 0
	.word 0
	.word 0
	.word 0
	.word 0
	.word 0
	.word 0

.section .text

.global isr_reset

isr_reset:

	bl motor_entry

$ make dump
  ODUMP  bldc.elf

bldc.elf:     file format elf32-littlearm


Disassembly of section .isr:

20000000 <ld_sisr>:
20000000:       00000000        andeq   r0, r0, r0
20000004:       20000000        andcs   r0, r0, r0
        ...

Disassembly of section .text:

20000000 <isr_reset>:
20000000:       f000 f800       bl      20000004 <motor_entry>

20000004 <motor_entry>:
20000004:       e7fe            b.n     20000004 <motor_entry>
        ...