Здравствуйте.

Компания , которая известна в Силиконовой Долине, и с хорошей репутацией набирает на работу 5-8 человек и готова спонсировать рабочую визу H1 кандидатам. Открыты позиции в двух направлениях. Контракт на 12 месяцев, который можно будет продлить до 24 месяцев и дольше. Английский язык - на уровне того, чтобы можно было общаться на рабочие темы. Зарплата от $45 в час и выше, взависимости от квалификации.

Пожалуйста, присылайте свои резюме только на английском языке. Манаджер не говорит по русски. это моя личная почта. Я не рекрутер, просто помогаю найти людей. nstefanioutine@gmail.com

Кандидаты должны отвечать требованиям в описании работы.

Пожалуйста, когда присылаете резюме , в шапке напишите, на что аппликаетесь.

Спасибо

Position 1: ASIC Synthesis and STA Engineer

Position : ASIC Synthesis and STA Engineer
Location: San Jose, CA
Duration: 12 Months , could extend to 24 plus months
Competitive salary
H1 Visa sponsored
Acceptable communication skills
Minimum Experience: 5 years

• Logic Synthesisl and STA experience on high speed SOC designs
• Knowledge about industry standards and practices in constraint verification and validation, Physically aware synthesis, and Timing closures.
• Experience in developing and implementing multi-mode/multi-corner STA constraints.
• Solid Understanding of all aspects of Timing flow, Physical construction and Integration.
• Working Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes.
• Power user of industry standard Timing ,Physical Design & Synthesis tools.
• Generate block level static timing constraints.
• Close timing on critical blocks by working with RTL, PD teams.
• Perform Timing optimization and validate the design for functionality.
• Generate and Implement ECOs to fix timing etc.
• Run Timing verification flow at chip/block level and provide guidelines to fix violations to other designers and/or perform the fixes.
• Solid Understanding of scripting languages such as Perl/Tcl
• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required.

Position 2: Sr.DFT Engineer

Position : Sr. DFT Engineer Location: San Jose, CA
Duration: 12 Months , could extend to 24 plus months
Competitive salary
H1 Visa sponsored
Acceptable communication skills
Minimum Experience: 5 years

• Excellent knowledge of latest state-of-the-art trends in DFT and test.
• Hands-on design and verification experience with JTAG protocols, Scan and BIST architectures, including Logic BIST, memory BIST, IO BIST
• Verification skills include Logic Equivalency checking and validating the test-timing of the design.
• Experience working with Gate level SDF back annotated simulation and debug with logic simulators.
• Experience with DFT silicon sign-off for tape out.
• Post-silicon validation and debug experience; Ability to work with ATE patterns.
• Strong verbal communication skills and ability to thrive in a dynamic environment.
• Great RTL design, verification, debug and scripting skills with minimal oversight.
• Scripting skills: Tcl/Perl
• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required