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6.7
Boot Sequence
The device requires that SYSRSTn stay asserted for at least 300 μs after power and clocks are
stable. The following procedure describes the boot sequence starting with the reset assertion:
1. While SYSRSTn is asserted, the CPU PLL and the core PLL are locked.
2. Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK
cycles.
3. If Serial ROM initialization is enabled, an initialization sequence is started.
4. If configured to boot from NAND flash (and BootROM is disabled), the device also performs a
NAND Flash boot sequence to prepare page 0 in the NAND flash device for read.

Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts
executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according
to sample at reset setting, see Table 32, Reset Configuration, on page 67.

For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281
Functional Specifications.

As part of the CPU boot code, the CPU typically performs the following:
Configures the PCI Express address map.
Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization
(sets <InitEn> bit [0] to 1 in the SDRAM Initialization Control register).
Sets the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.